![]() ![]() This tells us the number of shifts that need to be performed in order to reconstruct the floating-point number from IEEE format. The exponent value comes from the length that the most-significant 1-bit is in. This gives us a complete mantissa value for the result. ![]() If there are, we should round the last bit of the mantissa to 1. If the RHS value gets shifted too far to the right and we lose precision, we need to check if there are any 1-bits to the right of where the value gets cut off. Since we stored our fraction starting in the MSB, we take the value from that register, shift it to the right however many binary digits the left value takes up, and OR the mantissa LHS value with the RHS fraction. The RHS fractional value must be combined with the LHS value already stored in the result register. Then we apply the AND operation to the mask and the LHS value, and shift the result into the most significant bit for the mantissa value (position 22). To get the mantissa value, if there is a value in the left-hand argument, we find the most significant 1-bit and create a bit mask that is the length of the value excluding the most significant 1-bit. Knowing this value allows us to treat the integer value like a decimal so that we can use a doubling technique to find its binary fractional approximation. We do this by finding a power of 10 that is greater than the RHS argument. The RHS is passed in as an integer, so we need to convert it to a binary fraction. We convert the left-hand argument to a positive binary number even if it was stored as a negative (2’s compliment). ![]() The following approach was used to generate a floating point number: The following article discusses exactly what a floating point number is. A simple routine in Verilog HDL that converts integers into IEEE 754 Floating Point format. ![]()
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